HP annouced yesterday that they have completed research that could lead to the creation of field programmable gate arrays (FPGAs) up to eight times denser, yet using less energy for a set computation than those currently produced.
But not only that, but the chips could be created using the same size transistors as those used in the current FPGA design, which would mean producing them would only require minimal modifications to existing fabrication facilities.
"FPGAs are integrated circuits with programmable logic components and interconnects that can be adapted by end-users for specific applications. They are used in a wide range of industries, including communications, automotive and consumer electronics."
The way the tech works is by layering a nanoscale crossbar switch structure on top of conventional conventional CMOS.
This is done using an Architecture that the researchers from HP Labs have named
"Field Programmable nanowire interconnect" - and of course the compulsory acronym FPNI
The paper on the research - by Greg Snider and Stan Williams - will be featured in the Jan. 24 issue of Nanotechnology - published by the british institute of Physics.
According to Williams HP is working on producing an actual chip using the approach and could have a laboratory prototype completed within the year.
“As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics,” said Williams, an HP Senior Fellow and director, Quantum Science Research, HP Labs. “Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”
In the FPNI approach, all logic operations are performed in the CMOS, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer. Since conventional FPGAs use 80 to 90 percent of their CMOS for signal routing, the FPNI circuit is much more efficient; the density of transistors actually used for performing logic is much higher and the amount of electrical power required for signal routing is decreased.
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Comment by Ronan Murphy, on 21-Apr-2007 02:36
What is the current understanding of the number of years Moore's Law will still be applicable using conventional chip fabrication techniques?