The processor is Samsung S3C2410 (ARM920T based), and the IIS interface on this Samsung processor provides DMA transfer mode for FIFO access (since FIFO does not support interrupt but DMA). The driver needs to control data transmitting and receiving simultaneously. The IIS interface is in slave mode, the codec will generate all clocks, and the FS signal of this clock may be from 7.2k to 10.287kHz. The driver needs to schedule a task for kernel application when certain samples received.
We want to know if anyone can write this codec driver for us.
We are using TDK1903 codec.
We need this project done in a week or 10 days at most. Please let us know if this can be done in a week to 10 days. Also please quote us the price.
Looking forward to hear from you soon
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