Hi All,

I have successfully implemented  an ADC on this silicon, but am having issues with the input voltage range.

Currently I am achieving 1..2V input, and it works very well over that range, but I thought this FPGA had a common mode range that went to GND?

Anyone know any better? .... or is it only some other Lattice FPGA's that have a better LVDS common mode range.

Thanks,

Bernie